- User Since
- Oct 14 2014, 10:43 PM (217 w, 1 d)
Jul 23 2018
and new photo of old power board for archives :)
Apr 17 2018
The main focus will be on I2C, SPI and GPIO signals, where the latter ones should have predictable delays because they might control timing sensitive signals (exposure control, trigger, etc). There is no need to handle large bandwidth or complex communication like AMBA here.
Mar 20 2018
Mar 13 2018
Mar 4 2018
@malita With HDMI know-how we mean that you have a basic understanding how HDMI works, how the data is encoded and transported between source and sink and what the building blocks of an HDMI image are ... Tim does a nice overview of HDMI here https://media.ccc.de/v/33c3-8057-dissecting_hdmi
Feb 27 2018
Is the foam ESD safe?
Is it conductive?
@davidak can do, but what structure and location do we want for those?
Feb 23 2018
@RexOr Note that the symbol you are using as 'beta' is most likely an sz ligature (or sharp s) and not a greek beta as the beta does not have a serif or swash at the bottom while the long s from sz has.
Feb 21 2018
CE is mandatory for certain classes of equipment which we might or might not fall into, depending on the setup.
Those are GPL v2.0.
Feb 8 2018
Great! Please complete the coding challenge and write a GSoC 2018 application.
Jan 28 2018
Jan 23 2018
Nov 14 2017
Nov 5 2017
Do you have any documentation about the UHS-III physical layer?
Oct 28 2017
Note that we are using Eagle 7.7.0 which is basically the last offline/old-license version before Autodesk took over.
Also note that our long term plan includes switching to KiCad which has made great progress since it gets the CERN treatment.
Jul 18 2017
27.9g for the footplate and 47.9g for the mountbase/skeleton.
May 23 2017
Is it possible to record in Uncompressed 4K 4:3 CinemaDNG internally?
Yes, but only for a short period, till the memory is full.
Apr 30 2017
Apr 2 2017
So, let's look into two example cases:
Sounds nice and should be doable on the MicroZed.
It might be worth using decimation and keeping the framerate to avoid extensive buffering.
The obvious drawback is that connectivity via ethernet is lost.
Still doesn't make any sense to me, as there never is any missing data for any channel.
Was this further investigated since?
Very likely, but I guess we have to simply test this on a real system.
Mar 29 2017
@mash: while that is a good idea for cutting/post software, this is not an option for the AXIOM Beta as there is no GPU to accelerate anything.
It is unlikely that the lens system manufacturers will disclose the information about their lenses, but of course, it is worth a try contacting and asking them.
Mar 24 2017
The implementation has to be done on both FPGAs (Xilinx ZYNQ and Lattice MachXO2).
As this is a FOSS/OH project, you have to limit the design to IP without restrictions on both sides.
Using platform specific primitives like DDR I/O, SerDes or FIFOs is not as problem, as long as they are variants to a generic entity (which can be adapted to a new platform with little to none effort).
Mar 23 2017
@kkvasan92: AXI is not required/desired for simulation/emulation.
@anil: With Link Training we refer to training the LVDS connection required for the Gearwork.
Yes, we have IRC, it is on #apertus @ irc.freenode.
Just join there and ask if you need anything.
@sagnikbasu: Sorry for the delay, I obviously missed your questions.
Mar 16 2017
Forgot to say, the fingers look great!!!!
It looks to me like the CI palette features a number of similar pastel colours, so that would work without changing the colour tone on the boards too much. E.g. secondary set, third colour (the red) and ternary set, the last two colours should be almost perfect for the MicroZed and OSHpark boards. The plugins could use the green from the secondary or ternary set, whatever looks better.
Mar 15 2017
Mar 12 2017
Bi-directional communication between ZYNQ and MachXO2 over a single LVDS pair (half duplex) in one case and over two LVDS pairs (full-duplex) in the other case.
Note that there is also a single ended clock line which can (and probably should :) be used for synchronization.
I don't think that this needs to be Vendor specific in any way.
I.e. you can use the Xilinx Vivado toolchain or any other (Altera Quartus, Lattice Diamond, ...) for testing and simulation, but the resulting HDL should be vendor independent.
Mar 3 2017
Here a few quick comments far from being complete:
Mar 2 2017
Ah, I just realized that the shields have more holes (4) than in reality (2) which needs to be corrected.
Yes, the grey version looks really nice, so if the color version had the same lightness (or maybe a tad bit brighter) it would be almost perfect :)
Still missing the labels for each part, but I guess that will be added later as a separate layer?
Mar 1 2017
Feb 23 2017
I liked the strong perspective of the PCB-Stack-Concept-V03-022 and the colorized black ink style very much.
This one looks to much like a preview rendering for a photorealistic model.