To apply for this task please complete this mandatory coding challenge together with your application: T871
Applications without matching coding challenge completed will not be considered.
The AXIOM Beta will soon feature an USB 3.0 Plugin with a Lattic FPGA to transfer raw video data via USB.
- Implement gearwork and communication interface
- Implement link training
- Simulate/Test the interface and gearwork
- SERDES Know-How
- HDL (VHDL or Verilog)
To get in touch with any mentor check the Mentor Contact List.
Notes: If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.