USB Module Gearwork
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To apply for this task please complete this mandatory coding challenge together with your application: T871
Applications without matching coding challenge completed will not be considered.

The AXIOM Beta will soon feature an USB 3.0 Plugin with a Lattic FPGA to transfer raw video data via USB.


  • Implement gearwork and communication interface
  • Implement link training
  • Simulate/Test the interface and gearwork


  • SERDES Know-How

Language Skills:

  • HDL (VHDL or Verilog)

Difficulty: Medium

Mentors: Bertl

To get in touch with any mentor check the Mentor Contact List.

Notes: If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.

Related Objects

Bertl created this task.Jan 23 2018, 12:39 PM
Bertl updated the task description. (Show Details)
Bertl raised the priority of this task from to Needs Triage.
Bertl moved this task from Misc to FPGA / HDL on the Google Summer of Code 2019 board.
Bertl added a subscriber: Bertl.
Bertl renamed this task from USB Module HDL Gearwork to USB Module Gearwork.Jan 23 2018, 1:06 PM
Bertl changed the edit policy from "All Users" to "Administrators".
sebastian updated the task description. (Show Details)Mar 8 2018, 8:24 PM
sebastian changed the edit policy from "Administrators" to "All Users".Tue, Feb 5, 9:53 AM
BAndiT1983 updated the task description. (Show Details)Tue, Feb 5, 10:08 AM
sebastian triaged this task as Normal priority.Wed, Feb 6, 12:47 PM
Bertl updated the task description. (Show Details)Wed, Feb 6, 1:12 PM