To apply for this task please complete this mandatory coding challenge together with your application: T871
Applications without matching coding challenge completed will not be considered.
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The AXIOM Beta will soon feature an USB 3.0 Plugin with a Lattic FPGA to transfer raw video data via USB.
**Goals:**
- Implement gearwork and communication interface
- Implement link training
- Simulate/Test the interface and gearwork
**Prerequisites:**
- SERDES Know-How
**Language Skills:**
- HDL (VHDL or Verilog)
**Mentors:** Bertl
To get in touch with any mentor check the [[ https://www.apertus.org/GSoC-2018-Mentor-Contact-List | Mentor Contact List]].
**Notes:** If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.