Image Sensor Simulation/Emulation
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Create a Simulation/Emulation of the CMV12000 image sensor currently used in the AXIOM Beta so that the rest of the system can be tested/used without the actual image sensor hardware.


  • Generate Bitstream Test Data
  • Generate Fake Still Image Data
  • Generate Fake Video Data (in the range of 25 or 30 FPS)
  • Emulate Sensor Registers
  • Emulate Sensor Behaviour and Bitstreams


  • Basic image image sensor principles

Language Skills:

  • HDL (VHDL or Verilog)

Mentors: Bertl

To get in touch with any mentor check the Mentor Contact List.


Notes: If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.

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Bertl created this task.Feb 8 2017, 11:00 PM
Bertl updated the task description. (Show Details)
Bertl raised the priority of this task from to Needs Triage.
Bertl moved this task to Miscellaneous on the Google Summer of Code 2018 board.
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Bertl updated the task description. (Show Details)Feb 8 2017, 11:05 PM
sebastian updated the task description. (Show Details)Feb 8 2017, 11:10 PM
sebastian added a project: AXIOM Beta Software.
Bertl updated the task description. (Show Details)Feb 9 2017, 5:23 PM

Hi Mr Bertl,
Can i assume that xilinx tool flow will be used for hardware emulation As Xilinx zynq 7020 is used in AXIOM camera. uncompressed video or image data will be placed in memory and sensor model should generate output bit stream for that image/video according to timing and functional standard of the sensor, am i correct? is it possible to use available IPs ( opencore / xilinx) if it can be used?

Bertl added a comment.Mar 12 2017, 7:39 PM

I don't think that this needs to be Vendor specific in any way.
I.e. you can use the Xilinx Vivado toolchain or any other (Altera Quartus, Lattice Diamond, ...) for testing and simulation, but the resulting HDL should be vendor independent.

Image or video data will be available as input stream (different sources possible) and it is safe to assume that the sequence is sensel per row for each row from top to bottom.
Available IP can be used, as long as the license is FOSS/OH compatible (i.e. it can be used on any FPGA wihtout restrictions and the source is available).

Hope that clarifies,

PS: we should have a chat on IRC regarding the details and how it could be implemented/tested.

Thanks a lot for clarifying. I am interested in this project.
i need some more clarification

According to data sheet of CMV12000 image sensor which is used in AXIOM alpha camera, SPI interface is used for controls purpose and LVDS channels provide output frame. can you please tell the difference between fake image data and fake video data. I thought as fake video generator as multiple output frame from sensor model according to frames in video file.

Is it needed to model 4K pixel array by floating point registers model and doing AFE operation using floating operations or this task only concerned with sensor output timing specification and control registers values?

Regarding hardware emulation, can you please tell about interfaces
AXI can be used as input stream interface for hardware emulation model assuming this emulation sensor model going to be used in same fpga where main system going to be implemented?

Bertl added a comment.Mar 23 2017, 9:21 AM

@kkvasan92: AXI is not required/desired for simulation/emulation.

We want to simulate the sensor hardware, so it should produce similar/identical output to a real sensor.


Bertl updated the task description. (Show Details)Jan 23 2018, 12:42 PM
Bertl changed the edit policy from "All Users" to "Administrators".Jan 23 2018, 1:06 PM
sebastian updated the task description. (Show Details)Mar 8 2018, 8:24 PM
sebastian updated the task description. (Show Details)Mar 17 2018, 6:41 PM
sebastian updated the task description. (Show Details)