4K HDMI output HDL Gearwork Logic / IP Core
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Description

The AXIOM Beta will soon feature a Plugin with a Xilinx Artix FPGA with Gigabit Tranceivers to act as gearwork for the ZYNQ HDMI output.

Goals:

  • Implement gearwork and communication interface
  • Implement link training
  • Simulate/Test the interface and gearwork

Prerequisites:

  • HDMI Know-How
  • SERDES Know-How

Language Skills:

  • HDL (VHDL or Verilog)

Difficulty: Hard

Mentors: Bertl

Notes: If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.

sebastian created this task.Via WebFeb 8 2017, 4:04 PM
sebastian moved this task to FPGA on the Google Summer of Code 2017 workboard.
sebastian added a subscriber: sebastian.
Bertl changed the title from "4K HDMI output VHDL Logic / IP Core" to "4K HDMI output HDL Gearwork Logic / IP Core".Via WebFeb 9 2017, 4:43 PM
Bertl edited the task description. (Show Details)
sebastian triaged this task as "Normal" priority.Via WebFeb 9 2017, 4:56 PM
Bertl edited the task description. (Show Details)Via WebFeb 9 2017, 5:23 PM
anil added a subscriber: anil.Via WebMar 21 2017, 9:00 PM

Hi
I am Interested in this project.
Can you please elaborate on the project goals.
In the Goals, you mentioned Link training; are you referring to Link training, which is added in HDMI 2.1 spec?

Bertl added a subscriber: Bertl.Via WebMar 23 2017, 9:14 AM
Bertl added a comment.Via WebMar 23 2017, 9:19 AM

@anil: With Link Training we refer to training the LVDS connection required for the Gearwork.

The idea is to send high bandwidth data from the ZYNQ over the available LVDS channels to the FPGA on the Plugin.
To achieve maximum throughput (1-1.5Gbit/s for each LVDS pair), some kind of link training is required before actual data can be transmitted.

Hope that clarifies,
Herbert

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