To apply for this task please complete this mandatory coding challenge together with your application: T871
Applications without matching coding challenge completed will not be considered.
Read our Google Summer of Code Overview page:
The AXIOM Beta features two Lattice MachXO2 in addition to the Xilinx ZYNQ SoC which act as routing fabrics and extend the limited IOs from the main FPGA. The MachXO2s are connected via one or two LVDS pairs and share a common clock with the ZYNQ. A low latency high bandwidth bidirectional data transfer needs to be implemented and tested.
- Implement the physical layer with link training, bit and word alignment and direction change.
- Implement the communication layer and add bit error rate as well as latency checks.
- Optimize communication with encoding and SERDES, target bandwidth is 500Mbit/s.
- Serial Protocol Know-How
- Encoding Know-How
- HDL (VHDL, Verilog, nMigen)
To get in touch with any mentor check the Mentor Contact List.
Notes: If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.