Bidirectional Protocol for FPGA communication
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The AXIOM Beta features two Lattice MachXO2 in addition to the Xilinx ZYNQ SoC which act as routing fabrics and extend the limited IOs from the main FPGA. The MachXO2s are connected via one or two LVDS pairs and share a common clock with the ZYNQ. A low latency high bandwidth bidirectional data transfer needs to be implemented and tested.


  • Implement the physical layer with link training, bit and word alignment and direction change.
  • Implement the communication layer and add bit error rate as well as latency checks.
  • Optimize communication with encoding and SERDES, target bandwidth is 500Mbit/s.


  • Serial Protocol Know-How
  • Encoding Know-How

Language Skills:

  • HDL (VHDL, Verilog, nMigen)

Useful Links:

Difficulty: Hard

Mentors: Bertl

To get in touch with any mentor check the Mentor Contact List.

Notes: If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.

Related Objects

Bertl created this task.Feb 9 2017, 4:07 PM
Bertl updated the task description. (Show Details)
Bertl raised the priority of this task from to Needs Triage.
Bertl moved this task to FPGA / HDL on the Google Summer of Code 2022 board.
Bertl added a subscriber: Bertl.
Bertl updated the task description. (Show Details)Feb 9 2017, 5:23 PM

So I read the description of this project, I assume that the bi-directional communication protocol to be implemented in both the ZYNQ and Machxo2 side. In case of packet-oriented communication, should we implement an architecture similar to the UDP protocol, which I think will be best for large bandwidth video data?

Also, the bus mapping part, does it involve synchronous communication between the zynq and MachXo2 without any time slack?

Bertl added a comment.Mar 12 2017, 8:17 PM

Bi-directional communication between ZYNQ and MachXO2 over a single LVDS pair (half duplex) in one case and over two LVDS pairs (full-duplex) in the other case.
Note that there is also a single ended clock line which can (and probably should :) be used for synchronization.

We do not want to transfer large bandwidth data like video streams (at least not for now :) over this connection, instead we want to reach devices connected to the routing fabrics (MachXO2) in an efficient and, at least for some devices, timely deterministic way (i.e. with a fixed, known delay).

The packet architecture should probably be more like ATM, i.e. fixed size, small packets which can be categorized into three priorities: realtime (immediate), efficient (prioritized) and idle.
The highest priority (realtime) will only be used to map 'wires' which basically function as triggers to e.g. the sensor or similar and require a deterministic delay.
The second priority (efficient) is basically for all devices connected to remote bus systems (I2C, SPI, etc) which need to be accessed via the routing fabrics.
The lowest priority (idle) is for general information exchange like communicating error counters or collected status information which is neither time critical nor tied to a device.

Hope that clarifies,

danuka added a subscriber: danuka.Mar 23 2017, 4:25 PM
danuka added a comment.EditedMar 23 2017, 9:12 PM

Hi Bertl,
I am final year undergraduate of Electronic and Telecommunication Engineering, University of Moratuwa. I have gone through the description of the project that you are posted and I am clarifying on it. I have done many FPGA related projects and I am very interested in this field. I have few questions on this project.
• Do we have to implement the communication interface in the both Xilinx and lattice fpga platforms?
• If yes then will we be able to use the ip cores like xilincs fifos?
• Or else should it be a single implementation which can be run on both platforms?

Bertl added a comment.Mar 24 2017, 3:53 AM

The implementation has to be done on both FPGAs (Xilinx ZYNQ and Lattice MachXO2).
As this is a FOSS/OH project, you have to limit the design to IP without restrictions on both sides.
Using platform specific primitives like DDR I/O, SerDes or FIFOs is not as problem, as long as they are variants to a generic entity (which can be adapted to a new platform with little to none effort).

Hope that clarifies,

Bertl updated the task description. (Show Details)Jan 23 2018, 12:44 PM
Bertl changed the edit policy from "All Users" to "Administrators".Jan 23 2018, 1:07 PM
sebastian updated the task description. (Show Details)Mar 8 2018, 8:24 PM
ymc98 added a subscriber: ymc98.Mar 22 2018, 12:03 AM

Balance of generality and simplicity is essential and I recommend glancing at PCIe TLP packages.
Possibly a much-simplified version of this would work here.

Are you bridging existing protocols, like, say AXI4 or Avalon?

The main focus will be on I2C, SPI and GPIO signals, where the latter ones should have predictable delays because they might control timing sensitive signals (exposure control, trigger, etc). There is no need to handle large bandwidth or complex communication like AMBA here.


sebastian changed the edit policy from "Administrators" to "All Users".Feb 5 2019, 9:52 AM
BAndiT1983 updated the task description. (Show Details)Feb 5 2019, 10:08 AM
sebastian triaged this task as Normal priority.Feb 6 2019, 12:47 PM
Bertl updated the task description. (Show Details)Feb 6 2019, 1:11 PM
Bertl updated the task description. (Show Details)Mar 11 2019, 3:14 AM
sebastian updated the task description. (Show Details)Apr 6 2019, 12:36 PM
Bertl updated the task description. (Show Details)Mar 30 2020, 4:45 PM
sebastian updated the task description. (Show Details)Feb 18 2021, 6:47 PM
Bertl renamed this task from Bidirectional Packet Protocol for FPGA communication to Bidirectional Protocol for FPGA communication.Feb 20 2021, 3:12 PM
Bertl updated the task description. (Show Details)
NP95 added a subscriber: NP95.EditedMar 28 2021, 12:15 AM

Is this the page to discuss this project or is it being discussed on the mailing list as well. For some reason when I try to access the Archives of the mailing list I cannot access them. Also, my understanding of the project based on last GSOC is that the Packet layer is mostly done, it is the layers below that have to be optimized?

Also is there a way to know the current SERDES bandwidth? So far the only documentation I have studied is last year's project is there any other code and documentation other than the one mentioned in the post that I should be looking at?
(Edit 2: Is the VHDL codebase for the AXIOM Beta?

Edit: I just looked at the history of the description, it is a bit more clearer to me