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The AXIOM Beta features two Lattice MachXO2 in addition to the Xilinx ZYNQ SoC which act as routing fabrics and extend the limited IOs from the main FPGA. The MachXO2s are connected via a single LVDS pair and share a common clock with the ZYNQ. A Packet Protocol is required to utilize the bandwidth and support various bus protocols on the Lattice FPGAs (I2C, SPI, GPIO ...)
- Define a bidirectional packet oriented protocol which works over a single LVDS pair.
- Implement and test/simulate the packet oriented communication.
- Implement various bus mappings utilizing the new interface (I2C, SPI, GPIO, ...).
- Optimize communication with encoding and SERDES.
- Packet Protocol Know-How
- Encoding Know-How
- HDL (VHDL or Verilog)
To get in touch with any mentor check the Mentor Contact List.
Notes: If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.