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The AXIOM Beta has a huge number of FPGA related settings currently configured via AXI memory mappings.
This has a number of disadvantages like consuming huge amounts of resources both gate and routing wise and often creates unnecessary bottlenecks.
The basic idea is to use Dynamic Reconfiguration to change the settings during runtime directly where needed.

Goals:

• Implement a Frame Reconfiguration Interface via ICAP
• Create suitable HDL Entities for setting and retrieving values
• Simulate/Test the implementation

Prerequisites:

• Dynamic Reconfiguration Know-How

Language Skills:

• HDL (VHDL or Verilog)

Useful Links:

• https://github.com/SymbiFlow/prjxray
• https://www.eee.hku.hk/~hso/classes/rcclass/handouts/10-partialreconfig.pdf

Difficulty: Very Hard

Mentors: Bertl

To get in touch with any mentor check the Mentor Contact List.

Notes: If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.