Hi Bertl,
I am final year undergraduate of Electronic and Telecommunication Engineering, University of Moratuwa. I have gone through the description of the project that you are posted and I am clarifying on it. I have done many FPGA related projects and I am very interested in this field. I have few questions on this project.
• Do we have to implement the communication interface in the both Xilinx and lattice fpga platforms?
• If yes then will we be able to use the ip cores like xilincs fifos?
• Or else should it be a single implementation which can be run on both platforms?