Change Details

To apply for this task please complete this mandatory coding challenge together with your application: T871 Applications without matching coding challenge completed will not be considered. Read our Google Summer of Code Overview page: https://wiki.apertus.org/index.php/GSoC_Overview --- The AXIOM Beta will soon feature a Plugin with a Xilinx Artix FPGA with Gigabit Tranceivers to act as gearwork for the ZYNQ HDMI output. **Goals:** - Implement gearwork and communication interface - Implement link training - Simulate/Test the interface and gearwork **Prerequisites:** - HDMI Know-How - SERDES Know-How **Language Skills:** - HDL (VHDL or Verilog) **Useful Links:** - https://media.ccc.de/v/33c3-8057-dissecting_hdmi - https://en.wikipedia.org/wiki/SerDes **Difficulty:** Medium **Mentors:** Bertl To get in touch with any mentor check the [[ https://www.apertus.org/GSoC-2019-Mentor-Contact-List | Mentor Contact List]]. **Notes:** If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.

To apply for this task please complete this mandatory coding challenge together with your application: T871 Applications without matching coding challenge completed will not be considered. Read our Google Summer of Code Overview page: https://wiki.apertus.org/index.php/GSoC_Overview --- The AXIOM Beta will soon feature a Plugin with a Xilinx Artix FPGA with Gigabit Tranceivers to act as gearwork for the ZYNQ HDMI output. **Goals:** - Implement gearwork and communication interface - Implement link training - Simulate/Test the interface and gearwork **Prerequisites:** - HDMI Know-How - SERDES Know-How **Language Skills:** - HDL (VHDL or Verilog) **Useful Links:** - https://media.ccc.de/v/33c3-8057-dissecting_hdmi - https://en.wikipedia.org/wiki/SerDes - https://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf **Difficulty:** Medium **Mentors:** Bertl To get in touch with any mentor check the [[ https://www.apertus.org/GSoC-2019-Mentor-Contact-List | Mentor Contact List]]. **Notes:** If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.

To apply for this task please complete this mandatory coding challenge together with your application: T871 Applications without matching coding challenge completed will not be considered. Read our Google Summer of Code Overview page: https://wiki.apertus.org/index.php/GSoC_Overview --- The AXIOM Beta will soon feature a Plugin with a Xilinx Artix FPGA with Gigabit Tranceivers to act as gearwork for the ZYNQ HDMI output. **Goals:** - Implement gearwork and communication interface - Implement link training - Simulate/Test the interface and gearwork **Prerequisites:** - HDMI Know-How - SERDES Know-How **Language Skills:** - HDL (VHDL or Verilog) **Useful Links:** - https://media.ccc.de/v/33c3-8057-dissecting_hdmi - https://en.wikipedia.org/wiki/SerDes - https://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf **Difficulty:** Medium **Mentors:** Bertl To get in touch with any mentor check the [[ https://www.apertus.org/GSoC-2019-Mentor-Contact-List | Mentor Contact List]]. **Notes:** If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.