Change Details

To apply for this task please complete this mandatory coding challenge together with your application: T1228 Applications without matching coding challenge completed will not be considered. Read our Google Summer of Code Overview page: https://wiki.apertus.org/index.php/GSoC_Overview We are currently in the process of rewriting gateware for the axiom cameras in nMigen. (https://github.com/apertus-open-source-cinema/nmigen-gateware). Currently that efford only works on the micro but it would be beneficial if there was also support for running it on the Beta. Goals: * Implement a sensor interface for the CMV12k in nmigen * Implement a PHY (easy) * Translate the existing pixel remapper (which has a good architecture) from vhdl to nMigen * Implement a memorymapping SPI driver for the CMV12k control registers * Build a resolution loss debayerer that goes from 4k raw to FHD color * Build an "experiment" that implements a cmv12k to hdmi flow * Test everything on real hardware Prerequisites: * HDL & FPGA understanding Language Skills: * nMigen & Python Useful Links: * https://ams.com/cmv12000 * https://github.com/apertus-open-source-cinema/axiom-firmware/blob/master/peripherals/soc_main/pixel_remap.vhd * https://github.com/apertus-open-source-cinema/nmigen-gateware Difficulty: Hard Mentors: vup To get in touch with any mentor check the Mentor Contact List. Notes: If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.

To apply for this task please complete this mandatory coding challenge together with your application: T1228 Applications without matching coding challenge completed will not be considered. Read our Google Summer of Code Overview page: https://wiki.apertus.org/index.php/GSoC_Overview We are currently in the process of rewriting gateware for the axiom cameras in nMigen. (https://github.com/apertus-open-source-cinema/nmigen-gateware). Currently that efford only works on the micro but it would be beneficial if there was also support for running it on the Beta. **Goals**: * Implement a sensor interface for the CMV12k in nmigen * Implement a PHY with bit & word alignment * Translate the existing pixel remapper (which has a good architecture) from vhdl to nMigen * Implement a memorymapping SPI driver for the CMV12k control registers * Build a resolution loss debayerer that goes from 4k raw to FHD color * Build an "experiment" that implements a cmv12k to hdmi flow * Test everything on real hardware **Prerequisites**: * HDL & FPGA understanding **Language Skills**: * nMigen & Python **Useful Links**: * https://ams.com/cmv12000 * https://github.com/apertus-open-source-cinema/axiom-firmware/blob/master/peripherals/soc_main/pixel_remap.vhd * https://github.com/apertus-open-source-cinema/nmigen-gateware Difficulty: Hard Mentors: vup To get in touch with any mentor check the Mentor Contact List. Notes: If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.

To apply for this task please complete this mandatory coding challenge together with your application: T1228 Applications without matching coding challenge completed will not be considered. Read our Google Summer of Code Overview page: https://wiki.apertus.org/index.php/GSoC_Overview We are currently in the process of rewriting gateware for the axiom cameras in nMigen. (https://github.com/apertus-open-source-cinema/nmigen-gateware). Currently that efford only works on the micro but it would be beneficial if there was also support for running it on the Beta. **Goals:**: * Implement a sensor interface for the CMV12k in nmigen * Implement a PHY (easy)with bit & word alignment * Translate the existing pixel remapper (which has a good architecture) from vhdl to nMigen * Implement a memorymapping SPI driver for the CMV12k control registers * Build a resolution loss debayerer that goes from 4k raw to FHD color * Build an "experiment" that implements a cmv12k to hdmi flow * Test everything on real hardware **Prerequisites:**: * HDL & FPGA understanding **Language Skills:**: * nMigen & Python **Useful Links:**: * https://ams.com/cmv12000 * https://github.com/apertus-open-source-cinema/axiom-firmware/blob/master/peripherals/soc_main/pixel_remap.vhd * https://github.com/apertus-open-source-cinema/nmigen-gateware Difficulty: Hard Mentors: vup To get in touch with any mentor check the Mentor Contact List. Notes: If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.