Change Details

To apply for this task please complete this mandatory coding challenge together with your application: T871 Applications without matching coding challenge completed will not be considered. --- Create a Simulation/Emulation of the AXIOM Beta image sensor so that the rest of the system can be tested/used without the actual sensor hardware. **Goals:** - Generate Bitstream Test Data - Generate Fake Image Data - Generate Fake Video Data - Emulate Sensor Registers - Emulate Sensor Behaviour and Bitstreams **Prerequisites:** - Basic image sensor principles **Language Skills:** - HDL (VHDL or Verilog) **Mentors:** Bertl **Notes:** If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.

To apply for this task please complete this mandatory coding challenge together with your application: T871 Applications without matching coding challenge completed will not be considered. --- Create a Simulation/Emulation of the AXIOM Beta image sensor so that the rest of the system can be tested/used without the actual sensor hardware. **Goals:** - Generate Bitstream Test Data - Generate Fake Image Data - Generate Fake Video Data - Emulate Sensor Registers - Emulate Sensor Behaviour and Bitstreams **Prerequisites:** - Basic image sensor principles **Language Skills:** - HDL (VHDL or Verilog) **Mentors:** Bertl To get in touch with any mentor check the [[ https://www.apertus.org/GSoC-2018-Mentor-Contact-List | Mentor Contact List]]. **Notes:** If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.

To apply for this task please complete this mandatory coding challenge together with your application: T871 Applications without matching coding challenge completed will not be considered. --- Create a Simulation/Emulation of the AXIOM Beta image sensor so that the rest of the system can be tested/used without the actual sensor hardware. **Goals:** - Generate Bitstream Test Data - Generate Fake Image Data - Generate Fake Video Data - Emulate Sensor Registers - Emulate Sensor Behaviour and Bitstreams **Prerequisites:** - Basic image sensor principles **Language Skills:** - HDL (VHDL or Verilog) **Mentors:** Bertl To get in touch with any mentor check the [[ https://www.apertus.org/GSoC-2018-Mentor-Contact-List | Mentor Contact List]]. **Notes:** If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.