The AXIOM Beta will soon feature a Plugin with a Xilinx Artix FPGA with Gigabit Tranceivers to act as gearwork for the ZYNQ HDMI output.
**Goals:**
- Implement gearwork and communication interface
- Implement link training
- Simulate/Test the interface and gearwork
**Prerequisites:**
- HDMI Know-How
- SERDES Know-How
**Language Skills:**
- HDL (VHDL or Verilog)
**Difficulty:** Hard
**Mentors:** Bertl