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Sensor data comes in various configurations and does not always match the desired memory order.
The de-serialized data needs to be rearranged and repacked on the fly to provide a compact stream for the memory writers.
**Goals:**
- Implement remapping strategies for known sensors (CMV12000)
- Optimize for low gate count and high throughput
- Simulate/Test the re-mapper with test-streams
**Prerequisites:**
- Dual Memory know how
**Language Skills:**
- HDL (VHDL, Verilog, nMigen)
**Useful Links:**
- https://ams.com/documents/20143/36005/CMV12000_DS000603_1-00.pdf
- https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
**Difficulty:** Medium
**Mentors:** Bertl
To get in touch with any mentor check the [[ https://www.apertus.org/GSoC-2019-Mentor-Contact-List | Mentor Contact List]].
**Notes:** If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.