Change Details

VHDL logic to calculate/detect real time contrast/gradients (sobel) values from a frame Sobel: https://en.wikipedia.org/wiki/Sobel_operator This can be utilized for example for implementing autofocus or focus peaking. **References:** https://www.hindawi.com/journals/isrn/2013/820216/ http://ieeexplore.ieee.org/document/6949951/ **Goals:** - Implement line buffer - Implement pipelined (sobel) kernel **Prerequisites:** - FPGA Know-How **Language Skills:** - HDL (VHDL or Verilog) **Difficulty:** Easy to Medium **Mentor:** Alex, Herbert

To apply for this task please complete this mandatory coding challenge together with your application: T871 Applications without matching coding challenge completed will not be considered. --- VHDL image pipeline logic to calculate gradients and generate focus peaking information for real-time visualization. **Goals:** - Implement line buffer - Implement pipelined (sobel) kernel - Evaluate gradients for focus peaking **Prerequisites:** - FPGA Know-How - Image Processing Know-How **Language Skills:** - HDL (VHDL or Verilog) **References:** - https://www.hindawi.com/journals/isrn/2013/820216/ - http://ieeexplore.ieee.org/document/6949951/ - http://www.photolisticlife.com/2013/04/07/what-is-focus-peaking/ **Mentor:** Alex, Bertl

VHDL logic to calculate/detect real time contrast/gradients (sobel) values from a frame Sobel: https://en.wikipedia.org/wiki/Sobel_operator This can be utilized for example for implementing autofocus or focus peaking.To apply for this task please complete this mandatory coding challenge together with your application: T871 Applications without matching coding challenge completed will not be considered. --- **References:** https://www.hindawi.com/journals/isrn/2013/820216/VHDL image pipeline logic to calculate gradients and generate focus peaking information for real-time visualization. **Goals:** http://ieeexplore.ieee.org/docu - Implement/6949951/ **Goals:** line buffer - Implement pipeline bufferd (sobel) kernel - Implement pipelined (sobel) kernel- Evaluate gradients for focus peaking **Prerequisites:** - FPGA Know-How - Image Processing Know-How **Language Skills:** - HDL (VHDL or Verilog) **Difficulty:** Easy to MediumReferences:** - https://www.hindawi.com/journals/isrn/2013/820216/ - http://ieeexplore.ieee.org/document/6949951/ - http://www.photolisticlife.com/2013/04/07/what-is-focus-peaking/ **Mentor:** Alex, HerbertBertl