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We are currently in the process of rewriting gateware for the AXIOM cameras in Amaranth. (https://github.com/apertus-open-source-cinema/naps). It already has a system to dynamically declare registers that can be read / written over a external bus like AXI or JTAG. However wide busses like AXI require a lot of (routing) resources. To optimize the resource usage of the registers on the ZYNQ platform one can use a partial reconfiguration based system that does not need any extra routing resources. A prototype of this was already implemented by a former apertus intern: https://github.com/Swaraj1998/reg-test.
* Reproduce https://github.com/Swaraj1998/reg-test in Amaranth.
* Integrate a register backend based on this in the Amaranth-based gateware.
* Implement a pydriver version that uses this backed.
* Test on real hardware using the existing gateware targets
* Optimize the performance (read / write speed and resource usage)
* HDL & FPGA understanding
* Amaranth & Python
* VHDL (read & understand)
Mentors: vup, anuejn
To get in touch with any mentor check the [[ https://www.apertus.org/GSoC-Mentor-Contact-List | Mentor Contact List]].
Notes: If you do not have access to the required hardware platforms/dev kits, we will provide them (or remote access) to you for the duration of the project.