Complete this task as part of your GSoC 2018 application if you are applying for any FPGA related task.
This challenge is mandatory if you apply for T721, T728, T731, T733, T885 or T887.
Please choose at least one of the following tasks and make sure to adhere to the VHDL coding style used in the AXIOM Beta codebase.
Create VHDL code for a simple PWM controller and an I2C slave.
Make both separate and isolated entities which work together as an I2C slave PWM controller.
- Make PWM bit size and I2C slave address generics
- Control PWM setting via I2C register(s)
Create an UART - I2C bridge consisting of a simple UART and I2C master.
Make both separate and isolated entities which work together as a bidirectional bridge.
- Select a set of UART commands and responses to control generic I2C slaves.
- Make sure to handle slave responses properly and allow for a bus reset.
Create a high speed link (>500MHz) between two FPGAs utilizing SERDES and coding.
- Use PRNGs to test the link at real time and to estimate BER.
- Make sure to provision for a link reset and some kind of link training.
**Code for review:**
- @arun13e: https://github.com/arun13e/APERTUS-High_speed_link
To get in touch with any mentor check the [[ https://www.apertus.org/GSoC-2018-Mentor-Contact-List | Mentor Contact List]].