Complete this task as part of your GSoC 2020 application if you are applying for any FPGA related task.
This challenge is mandatory if you apply for T728, T731, T887, T1130 or T1131.
Please choose at least one of the following tasks and make sure to adhere to the VHDL coding style used in the AXIOM Beta codebase.
Create VHDL code for a serial to parallel converter (SERDES) which can be switched between 8, 10 and 12 bit.
Make sure that the implementation works at high serial speeds (600 MHz) and that the data word can be adjusted (bitslip).
- You can assume a clock with 100MHz and a fixed phase relation.
- You may use existing hardened units like PLL, DDR or SERDES to simplify the task.
- Test the resulting SERDES with simulation or on real hardware.
Create an UART - SPI bridge consisting of a simple UART and SPI master.
Make both separate and isolated entities which work together as a bidirectional bridge.
- Select a set of UART commands and responses to control generic SPI slaves.
- Make sure to handle different slave widths (e.g. 8 and 16 bit).
- Prepare for several (at least four) slave select signals.
Create a high speed link (>500MHz) between two FPGAs utilizing SERDES and coding.
- Utilize a common clock (e.g. 25MHz) between both FPGAs.
- Use PRNGs to test the link at real time and to estimate BER.
- Make sure to provision for a link reset and some kind of link training.
**//Example scenario for task 1://**
//An 8/10/12 bit serial ADC is connected to the FPGA over LVDS with a common 100MHz clock. The bitdepth can be selected via two control signals.
When the ADC is idle, it sends a test pattern 0xBAF (which is truncated to 8/10 bit in the 8 and 10bit modes) for link training and adjustment (bitslip).
When active, the ADC sends 50Msps for 12bit, 60Msps for 10bit and 75Msps for 8bit over the serial link. //
To get in touch with any mentor check the [[ https://www.apertus.org/GSoC-2019-Mentor-Contact-List | Mentor Contact List]].